The ARM® 64-bit processor systems are operable at multiple hierarchical privilege levels. Typically, such systems execute user applications at a lowest privilege level, known as exception level 0 (EL0), and execute system code at three increasingly higher privilege levels, known as EL1, EL2, and EL3. For example, operating system code may execute at EL1, hypervisor code for supporting virtual machines at EL2, and secure monitor code at EL3.
In processor architectures, such as the x86 architecture, non-maskable interrupts (NMIs) are supported. Generally, NMIs are high priority interrupts that cannot be ignored by system software, such as an operating system or hypervisor, even if other interrupts or exceptions are being ignored (or masked). Additionally, NMIs generally take priority over regular device interrupts. Non-maskable interrupts may be used, for example, to report system errors, for deadlock protection, to request performance of an action on short notice, and to implement other watchdog functionality.
Some processor architectures, such as the ARM64® architecture, do not support non-maskable interrupts. Porting a hypervisor or an operating system from an architecture that supports NMIs to an architecture that does not support NMIs may present challenges in implementing functionality based on NMIs (e.g., deadlock detection or performance counter overflows).